Regviz

Espressif Systems /ESP32-S3 /EFUSE /RD_REPEAT_DATA0

Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text

Interpret as RD_REPEAT_DATA0

Share

Cut and paste this URL to share the unmodified register and value:

https://regviz.com/r/Espressif Systems/ESP32-S3/EFUSE/RD_REPEAT_DATA0#0x0

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0RD_DIS0 (DIS_RTC_RAM_BOOT)DIS_RTC_RAM_BOOT 0 (DIS_ICACHE)DIS_ICACHE 0 (DIS_DCACHE)DIS_DCACHE 0 (DIS_DOWNLOAD_ICACHE)DIS_DOWNLOAD_ICACHE 0 (DIS_DOWNLOAD_DCACHE)DIS_DOWNLOAD_DCACHE 0 (DIS_FORCE_DOWNLOAD)DIS_FORCE_DOWNLOAD 0 (DIS_USB)DIS_USB 0 (DIS_CAN)DIS_CAN 0 (DIS_APP_CPU)DIS_APP_CPU 0SOFT_DIS_JTAG 0 (DIS_PAD_JTAG)DIS_PAD_JTAG 0 (DIS_DOWNLOAD_MANUAL_ENCRYPT)DIS_DOWNLOAD_MANUAL_ENCRYPT 0USB_DREFH 0USB_DREFL 0 (USB_EXCHG_PINS)USB_EXCHG_PINS 0 (EXT_PHY_ENABLE)EXT_PHY_ENABLE 0BTLC_GPIO_ENABLE 0 (VDD_SPI_MODECURLIM)VDD_SPI_MODECURLIM 0VDD_SPI_DREFH

Description

BLOCK0 data register 1.

Fields

RD_DIS

Set this bit to disable reading from BlOCK4-10.
DIS_RTC_RAM_BOOT

Set this bit to disable boot from RTC RAM.
DIS_ICACHE

Set this bit to disable Icache.
DIS_DCACHE

Set this bit to disable Dcache.
DIS_DOWNLOAD_ICACHE

Set this bit to disable Icache in download mode (boot_mode[3:0] is 0, 1, 2, 3, 6, 7).
DIS_DOWNLOAD_DCACHE

Set this bit to disable Dcache in download mode ( boot_mode[3:0] is 0, 1, 2, 3, 6, 7).
DIS_FORCE_DOWNLOAD

Set this bit to disable the function that forces chip into download mode.
DIS_USB

Set this bit to disable USB function.
DIS_CAN

Set this bit to disable CAN function.
DIS_APP_CPU

Disable app cpu.
SOFT_DIS_JTAG

Set these bits to disable JTAG in the soft way (odd number 1 means disable ). JTAG can be enabled in HMAC module.
DIS_PAD_JTAG

Set this bit to disable JTAG in the hard way. JTAG is disabled permanently.
DIS_DOWNLOAD_MANUAL_ENCRYPT

Set this bit to disable flash encryption when in download boot modes.
USB_DREFH

Controls single-end input threshold vrefh, 1.76 V to 2 V with step of 80 mV, stored in eFuse.
USB_DREFL

Controls single-end input threshold vrefl, 0.8 V to 1.04 V with step of 80 mV, stored in eFuse.
USB_EXCHG_PINS

Set this bit to exchange USB D+ and D- pins.
EXT_PHY_ENABLE

Set this bit to enable external PHY.
BTLC_GPIO_ENABLE

Bluetooth GPIO signal output security level control.
VDD_SPI_MODECURLIM

SPI regulator switches current limit mode.
VDD_SPI_DREFH

SPI regulator high voltage reference.

Links

()

Register License

Copyright 2024 Espressif Systems (Shanghai) PTE LTD

Licensed under the Apache License, Version 2.0 (the “License”); you may not use this file except in compliance with the License. You may obtain a copy of the License at

http://www.apache.org/licenses/LICENSE-2.0

Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License.

 ()

Register Reference

https://github.com/cmsis-svd/cmsis-svd-data